1. Field of the Invention
The present invention relates to an output buffer for transferring data stored in memory cells within a memory array to external devices. An output buffer might be included in a semiconductor memory such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a dual-port DRAM, and the like.
2. Description of the Prior Art
Output buffers for transferring data stored in memory cells in a semiconductor memory device to external devices typically comprise a CMOS circuit including P channel MOS (PMOS) transistors and N channel MOS (NMOS) transistors. FIG. 1 is a circuit diagram for a CMOS output buffer 10. Node I/O generates the output of the CMOS buffer in accordance with the conductance states of PMOS output transistor 13 and the NMOS output transistor 16. The CMOS output buffer can generate a high level data output ("1") when the PMOS output transistor 13 is ON and a low level data output ("0") when the NMOS output transistor 16 is ON.
PMOS output transistor 13 acts as the drive element for generating high level data "1" at output node I/O during the buffer's output mode of operation. The source of transistor 13 is connected to the power source potential Vcc and the drain of transistor 13 is connected to the output node I/O. The gate of output transistor 13 is connected to node V1 so that the potential at node V1 determines the conductance state of PMOS output transistor 13. For example, when the node V1 is precharged to a high level "1", transistor 13 is switched OFF, does not conduct, and the buffer cannot output a high level output signal. On the other hand, when a high level signal is to be output from the node I/O, the node V1 is discharged to a low level "0" so that the PMOS transistor 13 is ON and charges the node I/O to a high value "1". The potential at node V1 is determined by the conductance states of PMOS transistor 11 and NMOS transistor 12, which transistors are connected in series between a power source potential Vcc and a ground potential Vss. The source of the PMOS transistor 11 is connected to the power source potential Vcc and its drain is connected to the node V1. The source of the NMOS transistor 12 is connected to the ground potential Vss and the drain of the NMOS transistor 12 is connected to the node V1. A first control signal VA is supplied to the gates of both the PMOS transistor 11 and the NMOS transistor 12 to control the conductance states of transistors 11 and 12. For example, when the first control signal VA is held low, PMOS transistor 11 conducts and charges the node V1 to the high level "1", which places PMOS output transistor 13 in the non-output operation mode. When the first control signal VA is high, NMOS transistor 12 conducts, discharges V1 to a low level and places PMOS output transistor 13 in the output mode of operation. Thus, PMOS transistor 11 acts as a drive element for precharging node V1 to a high level "1+ and NMOS transistor 12 acts as a drive element for generating a low level "0".
NMOS output transistor 16 acts as a drive element for setting the node I/O to the low level "0" data during the output operation mode of the FIG. 1 buffer. The source of the NMOS output transistor 16 is connected to the ground potential Vss. The drain of the NMOS output transistor 16 is connected to the node I/O in common with the drain of the output transistor PMOS 13. Signals present at node V2 determine the potential present on the gate of the NMOS output transistor 16 and so control the transistor's conductance state. The potential on node V2 is determined by the conductance states of PMOS transistor 14 and NMOS transistor 15, which transistors are connected in series between the power source potential Vcc and the ground potential Vss. The source of the PMOS transistor 14 is connected to the power source potential Vcc and the drain of the PMOS transistor 14 is connected to the node V2. The source of the NMOS transistor 15 is connected to the ground potential Vss and the drain of the NMOS transistor 15 is connected to the node V2. The PMOS transistor 14 acts as a drive element for setting node V2 to the high level during the buffer's output operation mode and NMOS transistor 15 acts as a drive element for precharging the node V2 to the low level during the non-output operation mode. The second control signal VB, which is at the high level "1" during the buffer's non-output operation mode, is supplied to the gates of both the PMOS transistor 14 and the NMOS transistor 15.
The operation of the output buffer 10 having the configuration described above will now be explained. In the non-output operation mode of the buffer, a low "0" first control signal VA is supplied to the gates of both the PMOS transistor 11 and the NMOS transistor 12 so that a low level signal is supplied to the gate of the output PMOS transistor 13, placing PMOS transistor 13 in the OFF state. A high "1" value of the second control signal VB is supplied to the gates of PMOS transistor 14 and NMOS transistor 15, causing a low value of the signal V2 to be present on the gate of the NMOS output transistor 16 so that the output transistor 16 is OFF. Since output transistors PMOS 13 and NMOS 16 are both in the OFF state, the output node I/O is in a high impedance state where the output node I/O does not provide output data. The output node I/O provides neither "1" data nor "0" output data so long as the first control signal VA is low "0" and the second control signal VB is high "1".
The buffer 10 is switched to the output operation mode by switching either one of the first and second control signals VA and VB. Specifically, the buffer switches to a state where it outputs a high level "1" at output node I/O when the second control signal VB is held at the high level "1" and the control signal VA is switched from the low level "0" to the high level "1". The buffer 10 outputs low level data "0" at the I/O node when the first control signal VA is held at the low level "0" and the second control signal VB switches from the high level "1" to the low level "0".
For the buffer's high level data "1" output operation, a high level "1" signal VB is supplied to the gates of both the PMOS transistor 14 and the NMOS transistor 15 in the same manner as in the non-output operation mode, so that a low level "0" V2 is supplied to the gate of NMOS output transistor 16 and the output transistor 16 remains in the OFF state. Because the gate voltage potential VA of PMOS transistor 11 and NMOS transistor 12 is changed from the low level "0" to the high level "1", the supply of the power potential Vcc to the node V1 is switched off, and the electric potential of the node V1 switches from the high level "1" to the low level "0" as current flows from node V1 to the ground potential Vss. As a result, the low level "0" is supplied to the gate of the output transistor PMOS 13, the power supply potential Vcc is provided to the output node I/O, and the output node I/O outputs high level data "1".
When the buffer outputs low level data "0", a low level signal "0" VA is provided to the gates of PMOS transistor 11 and NMOS transistor 12 in the same manner as during the non-output operation mode, so that the high level "1" V1 is supplied to the output transistor PMOS 13, which remains in the OFF state. Signal VB switched from the high level "1" to the low level "0", switching the conductance states of PMOS transistor 14 and NMOS transistor 15. Consequently, the current path from the node V2 to the ground potential Vss is cut, and the node V2 charges from the low level "0" to the high level "1" as the power source potential Vcc is supplied to the node V2. As a result, the high level "1" is supplied to the gate of the output transistor NMOS 16, a current path is formed from the output node I/O to the ground potential Vss, and the electric potential of the output node I/O is changed to the low level "0".
The conventional output buffer 10 comprising CMOS circuits having the configuration shown in FIG. 1 can display certain undesirable characteristics. With increasing bit densities in products such as memory devices, the problems with output noise produced by buffers such as those illustrated in FIG. 1 have increased. The magnitude of the output noise is largely dependent on the magnitude of the time rate of change of the current flow in the output transistor, specifically, the size of the derivative dI/dt. Attempts to reduce the output noise signal by simply reducing the size of the derivative dI/dt can, however, unacceptably slow the switching speed of the output buffer.
FIG. 2 illustrates a semiconductor device formed on a chip which includes an output buffer 10 as shown in FIG. 1. In FIG. 2, PMOS transistor 19 acts as an output transistor for driving output node I/O with high level data "1", and NMOS transistor 22 acts as an output transistor for driving output node I/O with low level data "0". Capacitor "C0" represents an internal capacitance connected between an internal power supply Vcc-chip of the chip and an internal ground potential level Vss-chip of the chip. Reference characters L1 and L2 denote internal inductances that exist along the along the wiring lines that couple terminals 17 and 18 to the rest of the chip. Because the external power supply Vcc is provided to terminals 17 and 18, inductances L1 and L2 act to prevent Vcc-chip and Vss-chip from corresponding to Vcc and Vss-external, when one or the other of the voltages or grounds is subject to variations. A reference character C1 represents an output load capacitance between an I/O pad 21, connected to output node I/O of the chip, and an external ground potential Vss-ext.
In an output operation for the FIG. 2 circuit, a voltage dI/dt is produced when either of the output transistors PMOS 19 or NMOS 22 is switched to an ON state. For example, when low level data "0" is output at node I/O, the output transistor NMOS 22 switches ON and a voltage dI/dt is produced. Because the current flowing through NMOS 22 changes, a voltage dI/dt is produced across the inductor L2 which is connected between the external ground potential Vss and the internal ground potential Vss-chip. The potential difference V3=dI/dt across the inductor L2 causes the internal ground potential Vss-chip to rise in comparison with the external ground potential Vss-ext. Clock signal levels for the chip vary with variations in the external ground potential Vss-ext by an amount equal to the swing (noise) of the internal power of the chip, i.e., the voltage V3=dI/dt that appears across inductor L2. It is possible that the clock signals can vary to such an extent that the clock signals are not correctly recognized within the chip. Accordingly, the swing in the internal power of the chip should be kept small, and for this reason the dI/dt which flows in the output transistors of the output buffer during switching should also be kept small.
Conventionally, dI/dt is kept small in the buffer circuit of FIG. 1 by minimizing the width W of the NMOS transistor 12 when the output buffer generates high level data "1", and by minimizing the width W of the PMOS transistor 14 when the output buffer generates the low level data "0". The effect of reducing the width of the NMOS transistor 12 and the PMOS transistor 14 is to reduce the rate of change dV/dt of the voltages V1 and V2 applied to the gates of the output transistors 13 and 16, respectively. When dV/dt is small for V1 and V2, the rate of change dI/dt of the current flowing through the output transistor (13 or 16) being switched ON is maintained small. However, when dV/dt of V1 or V2 is maintained small, the current flowing through node V1 or the node V2 is also small. Thus, the time required until the output transistor switches ON and the buffer outputs a signal becomes large. This is undesirable because it reduces the switching speed of the buffer.
To reduce the rate of change dI/dt of the current flowing at the output node I/O and, consequently, the magnitude of the output noise, it is necessary to limit the change of the gate potential of the output transistor (i.e., either dV1/dt or dV2/dt) during the portion of the switching transition when the output transistor is ON. In other words, dV1/dt or dV2/dt must be limited only for the portion of the switching transition during which the gate voltage V1 or V2 for the respective output transistor 13 or 16 is greater than the threshold voltage for that output transistor. Regardless of this, to reduce the output noise for the conventional output buffer circuit shown in FIG. 1, the rate of change of the gate voltage potential V1 or V2 is kept small during switching in the time period where the output transistor 13 or 16 is not yet ON. The amount of time required until the output transistor 13 or 16 comes ON increases in accordance with the amount that the rate of change of the gate voltage of the output transistor decreases. Consequently, the output noise of a conventional buffer circuit cannot be reduced without undesirably increasing the memory access time.